1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of protecting elevated polysilicon structures during etching processes.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit elements that substantially determine performance of the integrated circuits. Such field effect transistors are frequently employed in making so-called “logic” circuits on a chip containing the integrated circuits. Such integrated circuit chips also may include many memory devices, such as Dynamic Random Access Memory (DRAMs) devices.
In fact, many modern integrated circuit chips may have one or more “logic regions” where primarily logic circuits or logic devices are made and one or more “memory regions or arrays” that primarily contain memory devices. Although the logic devices and memory devices are typically formed on the same chip, and they frequently share common materials, such devices do have fundamental structural differences, and they may typically be formed at different times during a particular process flow that is performed to form the completed integrated circuit device.
As one specific example, a logic circuit may typically be formed using a multitude of field effect transistors. A basic field effect transistor comprises a source region, a gate region and a channel region positioned between the source and drain regions. Such a transistor further includes a gate insulation layer positioned above the channel region and a gate electrode positioned above the gate insulation layer. When an appropriate voltage is applied to the gate electrode, the channel region becomes conductive and current may flow from the source region to the drain region. In many cases, the gate electrodes are made of polysilicon.
A typical DRAM device includes, among other things, a stack of layers. More specifically, a DRAM device typically includes a gate insulation layer, a so-called floating gate formed above the gate insulation layer, one or more layers of insulating material positioned above the floating gate and a control gate positioned above the latter layer of insulating material. In many cases, the control gate and the floating gate are made of polysilicon.
The basic structures of the field effect transistors and of the memory devices are typically formed by forming various layers of material and thereafter patterning those layers of material using known photolithography and etching processes. It is frequently the case that the basic layer stack for the memory devices, including the floating gate and the control gate, is formed prior to forming the gate electrodes for the transistors in the logic regions of the device. Typically, in patterning the gate electrodes for the logic devices, in one illustrative process flow, a tri-layer stack of materials is formed above the gate electrode material layer, typically polysilicon, in the logic regions, and above the previously formed stack of materials, including the floating gate and the control gate, for the memory devices in the memory regions. In one illustrative example, the tri-layer of materials is comprised of, for example, an organic dielectric layer (ODL) formed above the gate electrode material layer, an antireflective coating (ARC) layer positioned above of the ODL layer and a patterned layer of photoresist formed above the ARC layer.
Given the structural differences between the memory devices (which includes both a floating gate and a control gate) and the basic field effect transistors (which includes a single gate electrode) there is a significant topography difference between the memory regions and the logic regions, i.e., the basic memory stack is much taller than the stack of materials used to form the gate electrode structures in the logic areas. Unfortunately, this height difference may lead to the situation where the tri-layer of materials does not adequately cover or adequately protect the taller structures in the memory regions. That is, in some cases, certain features of the taller memory structures, e.g., the control gate that is comprised of polysilicon, may actually be damaged during the etching processes that are performed to define the gate electrodes for the logic devices. At best, such damage can reduce the electrical performance of the memory device and the circuits incorporating such devices, and, in a worst case scenario, depending upon the extent of the damage, may result in complete device failure.
The present disclosure is directed to various methods that may at least reduce or eliminate one or more of the problems identified above.